Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

3.5.6.1. Hierarchy Assignments

For a design with the hierarchy shown in the figure, which has failing paths in the timing analysis results similar to those shown in the table, mod_A is probably a problem module. In this case, a good strategy to fix the failing paths is to place the mod_A hierarchy block in a Logic Lock (Standard) region so that all the nodes are closer together in the floorplan.
Figure 32. Design Hierarchy
Table 10.  Failing Paths in a Module Listed in Timing Analysis
From To
|mod_A|reg1 |mod_A|reg9
|mod_A|reg3 |mod_A|reg5
|mod_A|reg4 |mod_A|reg6
|mod_A|reg7 |mod_A|reg10
|mod_A|reg0 |mod_A|reg2

Hierarchical Logic Lock (Standard) regions are also important if you are using an incremental compilation flow. Place each design partition for incremental compilation in a separate Logic Lock (Standard) region to reduce conflicts and ensure good results as the design develops. You can use the auto size and floating location regions to find a good design floorplan, but fix the size and placement to achieve the best results in future compilations.

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