Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

5.1.8. Viewing the Source and Destination of Placed Nodes

The Chip Planner allows you to view the registered fan-in or fan-outs of nodes in compiled designs with the Report Registered Connections task. This report is different from the Generate Fanin/Fanout connections report in that the source and destination nodes appear without connection lines, which may obscure the view.

  1. In the Chip Planner, select one or more nodes.
  2. In the Task pane, double-click Report Registered Connections.
  3. Select the options from the dialog box, and click OK.
The Reports pane displays the registered source and destination nodes. Turn on or off to switch visibility in the graphic view.
Figure 36. Report Registered Connections