Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

1.1. Device Considerations

All Intel® FPGAs have a unique timing model that contains delay information for all physical elements in the device, such as combinational adaptive logic modules, memory blocks, interconnects, and registers. The delays encompass all valid combinations of operating conditions for the target FPGA. Additionally, the device size and package determine pin-out and the resource availability.