Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents Using Partitions to Achieve Timing Closure

One technique to achieve timing closure is confining failing paths within individual design partitions, such that there are no failing paths passing between partitions. You can then use incremental make changes as necessary to correct the failing paths, and recompile only the affected partitions.

To use this technique:

  1. In the Design Partition Planner, load timing data by clicking View > Show Timing Data.
    Entities containing nodes on failing paths appear in red in the Design Partition Planner.
  2. Extract the entity containing failing paths by dragging it outside of the top-level entity window.
    • If there are no failing paths between the extracted entity and the top-level entity, right-click the extracted entity, and then click Create Design Partition to place that entity in its own partition.
  3. Keep failing paths within a partition, so that there are no failing paths crossing between partitions.
    If you are unable to isolate the failing paths from an extracted entity so that none are crossing partition boundaries, return the entity to its parent without creating a partition.
  4. Find the partition having the worst slack value. For all the other partitions, preserve the contents and set as Empty.
    For information about preserving the contents of a partition, refer to Incremental Block-Based Compilation Flow in the Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design .
  5. Adjust the logic in the partition and rerun the Fitter as necessary until the partition meets the timing requirements.
  6. Repeat the process for all other design partitions with failing paths.