Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

3.3.2.2.2. Insertion Delay

If a global signal is required, consider adding half a cycle to timing by using a negative-edge triggered register to generate the signal (top figure) and use a multicycle setup constraint (bottom figure).
Figure 24. Negative-Edge Triggered Register
Figure 25. Multicycle Setup Constraint
set_multicycle_path -from <generating_register> -setup -end 2 

Did you find the information on this page useful?

Characters remaining:

Feedback Message