Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

5.1. Design Floorplan Analysis in the Chip Planner

The Chip Planner simplifies floorplan analysis by providing visual display of chip resources. With the Chip Planner, you can view post-compilation placement, connections, and routing paths.
The Chip Planner allows you to:
  • Make assignment changes, such as creating and deleting resource assignments.
  • Perform post-compilation changes such as creating, moving, and deleting logic cells and I/O atoms.
  • Perform power and design analyses.
  • Implement ECOs.
  • Change connections between resources and make post-compilation changes to the properties of logic cells, I/O elements, PLLs, RAMs, and digital signal processing (DSP) blocks.

The Chip Planner showcases:

  • Logic Lock (Standard) regions
  • Relative resource usage
  • Detailed routing information
  • Fan-in and fan-out connections between nodes
  • Timing paths between registers
  • Delay estimates for paths
  • Routing congestion information