Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents Displaying Path Reports with the Timing Analyzer

The Timing Analyzer generates reports with information about all valid register-to-register paths. To view all timing summaries, double-click Report All Summaries in the Tasks pane.

If any clock domains have failing paths (highlighted in red in the Report pane), right-click the clock name listed in the Clocks Summary pane and select Report Timing to get more details.

When you select a path in the Summary of Paths tab, the path detail pane displays all the path information. The Extra Fitter Information tab offers visual representation of the path location on the physical device. This can reveal whether the timing failure is distance related, due to the source and destination node being too close or too far.

The Data Path tab displays the Data Arrival Path and the Data Required Path. You can determine the path segments contributing the most to the timing violations with the incremental information. The Waveform tab shows the signals in the time domain, and plots the slack between arrival data and required data.

The RTL Viewer or Technology Map Viewer provide schematic (gate-level or technology-mapped) representations of the design netlist, and can help you to assess which areas in a design can benefit from reducing the number of logic levels. To locate a timing path in one of the viewers, right-click a path in the timing report, point to Locate, and select either Locate in RTL Viewer or Locate in Technology Map Viewer. You can also investigate the physical layout of a path in detail with the Chip Planner.

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