Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

6.2.2. Saving a Node-Level Netlist

For non- Intel® Arria® 10 designs, you can preserve a node-level netlist in Verilog Quartus Mapping File (.vqm ) format.
You might need to preserve nodes if you use the Logic Lock (Standard) flow to back-annotate placement, import one design into another, or both. For all device families that support incremental compilation, you can use this feature to preserve compilation results.
Note: This feature does not support Intel® Arria® 10 devices.

Use the Export version-compatible database option to save synthesis results as an atom-based netlist in .vqm file format. By default, the Intel® Quartus® Prime software places the .vqm in the atom_netlists directory under the current project directory.

If you use the physical synthesis optimizations and want to lock down the location of all LEs and other device resources in the design with the Back-Annotate Assignments command, a .vqm file netlist is required. The .vqm file preserves the changes that you made to your original netlist. Because the physical synthesis optimizations depend on the placement of the nodes in the design, back-annotating the placement changes the results from physical synthesis. Changing the results means that node names are different, and your back-annotated locations are no longer valid.

You should not use an Intel® Quartus® Prime-generated .vqm file or back-annotated location assignments with physical synthesis optimizations unless you have finalized the design. Making any changes to the design invalidates your physical synthesis results and back-annotated location assignments. If you require changes later, use the new source HDL code as your input files, and remove the back-annotated assignments corresponding to the Intel® Quartus® Prime-generated .vqm file.

To back-annotate logic locations for a design that was compiled with physical synthesis optimizations, first create a .vqm file. When recompiling the design with the hard logic location assignments, use the new .vqm file as the input source file and turn off the physical synthesis optimizations for the new compilation.

If you are importing a .vqm file and back-annotated locations into another project that has any Netlist Optimizations turned on, you must apply the Never Allow constraint to make sure node names don’t change; otherwise, the back-annotated location or Logic Lock (Standard) assignments are invalid.

To preserve the nodes from Intel® Quartus® Prime physical synthesis optimization options for devices that do not support incremental compilation, perform the following steps:

  1. On the Assignments menu, click Settings. The Settings dialog box appears.
  2. In the Category list, select Compilation Process Settings. The Compilation Process Settings page appears.
  3. Turn onExport version-compatible database. This setting is not available for some devices.
  4. Click OK.