Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

6.1.2. Physical Synthesis Options

The Intel® Quartus® Prime software provides physical synthesis optimization options to improve fitting results. To access these options, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter).
Note: To disable global physical synthesis optimizations for specific elements of your design, assign the Netlist Optimizations logic option to Never Allow to the specific nodes or entities.
Table 22.  Physical Synthesis Options
Option Description
Perform asynchronous signal pipelining (no Intel® Arria® 10 support) Automatically inserts pipeline stages for asynchronous clear and asynchronous load signals during fitting to increase circuit performance. This option is useful for asynchronous signals that are failing recovery and removal timing because they feed registers using a high-speed clock. You can use this option if asynchronous control signal recovery and removal times are not achieving requirements. This option adds registers and potential latency to nets driving the asynchronous clear or asynchronous load ports of registers. The additional register delays can change the behavior of the signal in the design; therefore, you should use this option only if additional latency on the reset signals does not violate any design requirements. This option also prevents the promotion of signals to global routing resources.
Perform Register Duplication for Performance (no Intel® Arria® 10 support) Duplicates registers based on Fitter placement information to reduce the delay of one path without degrading the delay of another. You can also duplicate combinational logic when you enable this option. The Fitter can place the new logic cell closer to critical logic without affecting the other fan-out paths of the original logic cell. This setting does not apply to logic cells that are part of a chain, drive global signals, are constrained to a single LAB, or the Netlist Optimizations option set to Never Allow.
Perform Register Retiming for Performance (no Arria® 10 support) Enables the movement of registers across combinational logic, allowing the Quartus Prime software to trade off the delay between timing-critical paths and non-critical paths.
Perform Physical synthesis for combinational logic for Performance (no Intel® Arria® 10 support) Performs physical synthesis optimizations on combinational logic during synthesis and fitting to increase circuit performance. Swaps the look-up table (LUT) ports within LEs so that the critical path has fewer layers through which to travel. Also allows the duplication of LUTs to enable further optimizations on the critical path.
Physical Synthesis for Combinational Logic for Fitting (no Intel® Arria® 10 support)

Reduces delay along critical paths. This option swaps the look-up table (LUT) ports within LEs so that the critical path has fewer layers through which to travel. The option also allows the duplication of LUTs to enable further optimizations on the critical path. The option causes registers that do not have a Power-Up Level logic option setting to power up with a don't care logic level (X). When the Power-Up Don't Care option is turned on, the Compiler determines when it is beneficial to change the power-up level of a register to minimize the area of the design. A power-up state of zero is maintained unless there is an immediate area advantage. The registers contained in the affected logic cells are not modified. Inputs into memory blocks, DSP blocks, and I/O elements (IOEs) are not swapped. This setting does not apply to logic cells that are part of a chain, drive global signals, are constrained to a single LAB, or the Netlist Optimizations option set to Never Allow.

Perform WYSIWYG Primitive Resynthesis Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the setting specified in the Optimization Technique logic option.
Physical Synthesis Effort Level (no Intel® Arria® 10 support) Specifies the amount of effort, in terms of compile time, physical synthesis should use. Compared to the Default setting, a setting of Extra uses extra compile time to try to gain extra circuit performance. Conversely, a setting of Fast uses less compile time but may reduce the performance gain that physical synthesis is able to achieve.
Netlist Optimizations You can use the Assignment Editor to apply the Netlist Optimizations logic option. Use this option to disable physical synthesis optimizations for parts of your design.
Allow Register Duplication

Allows the Compiler to duplicate registers to improve design performance. When you enable this option, the Compiler copies registers and moves some fan-out to this new node. This optimization improves routability and can reduce the total routing wire in nets with many fan-outs.

If you disable this option, this disables optimizations that retime registers.

This setting affects Analysis & Synthesis and the Fitter.

Allow Register Merging

Allows the Compiler to remove registers that are identical to other registers in the design. When you enable this option, in cases where two registers generate the same logic, the Compiler deletes one register, and the remaining registers fan-out to the deleted register's destinations. This option is useful if you want to prevent the Compiler from removing intentional use of duplicate registers.

If you disable register merging, the Compiler disables optimizations that retime registers.

This setting affects Analysis & Synthesis and the Fitter.

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