Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

6.1.3. Perform Register Retiming for Performance

The Perform Register Retiming for Performance option enables the movement of registers across combinational logic, allowing the Intel® Quartus® Prime software to trade off the delay between timing-critical paths and non-critical paths. Register retiming can be done during Intel® Quartus® Prime integrated synthesis or during the Fitter stages of design compilation.
Figure 49. Reducing Critical Delay by Moving the Register Relative to Combinational Logic

Retiming can create multiple registers at the input of a combinational block from a register at the output of a combinational block. In this case, the new registers have the same clock and clock enable. The asynchronous control signals and power-up level are derived from previous registers to provide equivalent functionality. Retiming can also combine multiple registers at the input of a combinational block to a single register.

Figure 50. Combining Registers with Register Retiming

To move registers across combinational logic to balance timing, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter). Specify your preferred option under Optimize for performance (physical synthesis) and Effort level .

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