2. Optimizing the Design Netlist
This chapter describes how you can use the Intel® Quartus® Prime Netlist Viewers to analyze and debug your designs.
As FPGA designs grow in size and complexity, the ability to analyze, debug, optimize, and constrain your design is critical. With today’s advanced designs, several design engineers are involved in coding and synthesizing different design blocks, making it difficult to analyze and debug the design. The Intel® Quartus® Prime RTL Viewer, State Machine Viewer, and Technology Map Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.
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