Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

2.11. Viewing a Timing Path

After completing a full design compilation, including the timing analyzer stage, you can see a visual representation of a timing path cross-probe from a timing report. For details about generating the timing report, refer to the Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer .

When you locate the timing path from the Timing Analyzer to the Technology Map Viewer, the interconnect and cell delay associated with each node appears on top of the schematic symbols. The total slack of the selected timing path appears in the Page Title section of the schematic.

  1. To open the report from the Compilation Report Table of Contents, click Timing Analyzer GUI > Report Timing, and double-click the timing corner.
  2. To open the report from the Timing Analyzer, open the Report Timing folder in the Report pane, and double-click the timing corner.
  3. In the Summary of Paths tab, right-click a row in the table and select Locate Path > Locate in Technology Map Viewer. In the Technology Map Viewer, the schematic page displays the nodes along the timing path with a summary of the total delay.