Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

3.8. Timing Closure and Optimization Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2018.11.12 18.1.0
  • Updated "Placement Effort Multiplier" figure and text descriptions in "Adjust Placement Effort" topic.
  • Updated "Fitter Effort" figure and text descriptions in "Adjust Fitter Effort" topic.
  • Updated "Optimize Hold Timing Option" screenshot in "Wires Added for Hold" topic.
2018.09.24 18.1.0
  • Initial release in Intel Quartus Prime Standard Edition User Guide.
  • Removed duplicated topic: Resource Utilization Optimization Techniques. The topic is now in the Area Optimization chapter.
2017.11.06 17.1.0
  • Moved Topic: Design Evaluation for Timing Closure after Initial Compilation: Optional Fitter Settings.
  • Updated logic options about resource utilization optimization settings.
2017.05.08 17.0.0
  • Added topic: Critical Paths.
  • Updated Register-to-Register Timing and renamed to Register-to-Register Timing Analysis.
  • Renamed topic: Timing Analysis with the Timing Analyzer to Displaying Path Reports with the Timing Analyzer.
  • Removed (LUT-Based Devices) remark from topic titles.
  • Renamed topic: Optimizing Timing (LUT-Based Devices) to Timing Optimization.
  • Renamed topic: Debugging Timing Failures in the Timing Analyzer to Displaying Timing Closure Recommendations for Failing Paths.
  • Renamed topic: Improving Register-to-Register Timing Summary to Improving Register-to-Register Timing .
2016.05.02 16.0.0
  • Stated limitations about deprecated physical synthesis options.
  • Added information about monitoring clustering difficulty.
2015.11.02 15.1.0
  • Added: Periphery to Core Register Placement and Routing Optimization.
  • Changed instances of Quartus II to Quartus Prime.
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
  • Updated DSE II content.
June 2014 14.0.0
  • Dita conversion.
  • Removed content about obsolete devices that are no longer supported in QII software v14.0: Arria GX, Arria II, Cyclone III, Stratix II, Stratix III.
  • Replaced Megafunction content with IP core content.
November 2013 13.1.0
  • Added Design Evaluation for Timing Closure section.
  • Removed Optimizing Timing (Macrocell-Based CPLDs) section.
  • Updated Optimize Multi-Corner Timing and Fitter Aggressive Routability Optimization.
  • Updated Timing Analysis with the Timing Analyzer to show how to access the Report All Summaries command.
  • Updated Ignored Timing Constraints to include a help link to Fitter Summary Reports with the Ignored Assignment Report information.
May 2013 13.0.0
  • Renamed chapter title from Area and Timing Optimization to Timing Closure and Optimization.
  • Removed design and area/resources optimization information.
  • Added the following sections:

    Fitter Aggressive Routability Optimization.

    Tips for Analyzing Paths from/to the Source and Destination of Critical Path.

    Tips for Locating Multiple Paths to the Chip Planner.

    Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles.

November 2012 12.1.0
  • Updated “Initial Compilation: Optional Fitter Settings” on page 13–2, “I/O Assignments” on page 13–2, “Initial Compilation: Optional Fitter Settings” on page 13–2, “Resource Utilization” on page 13–9, “Routing” on page 13–21, and “Resolving Resource Utilization Problems” on page 13–43.
June 2012 12.0.0
  • Updated “Optimize Multi-Corner Timing” on page 13–6, “Resource Utilization” on page 13–10, “Timing Analysis with the Timing Analyzer” on page 13–12, “Using the Resource Optimization Advisor” on page 13–15, “Increase Placement Effort Multiplier” on page 13–22, “Increase Router Effort Multiplier” on page 13–22 and “Debugging Timing Failures in the Timing Analyzer” on page 13–24.
  • Minor text edits throughout the chapter.
November 2011 11.1.0
  • Updated the “Timing Requirement Settings”, “Standard Fit”, “Fast Fit”, “Optimize Multi-Corner Timing”, “Timing Analysis with the Timing Analyzer”, “Debugging Timing Failures in the Timing Analyzer”, “LogicLock Assignments”, “Tips for Analyzing Failing Clock Paths that Cross Clock Domains”, “Flatten the Hierarchy During Synthesis”, “Fast Input, Output, and Output Enable Registers”, and “Hierarchy Assignments” sections
  • Updated Table 13–6
  • Added the “Spine Clock Limitations” section
  • Removed the Change State Machine Encoding section from page 19
  • Removed Figure 13-5
  • Minor text edits throughout the chapter
May 2011 11.0.0
  • Reorganized sections in “Initial Compilation: Optional Fitter Settings” section
  • Added new information to “Resource Utilization” section
  • Added new information to “Duplicate Logic for Fan-Out Control” section
  • Added links to Help
  • Additional edits and updates throughout chapter
December 2010 10.1.0
  • Added links to Help
  • Updated device support
  • Added “Debugging Timing Failures in the Timing Analyzer” section
  • Removed Classic Timing Analyzer references
  • Other updates throughout chapter
August 2010 10.0.1 Corrected link
July 2010 10.0.0
  • Moved Compilation Time Optimization Techniques section to new Reducing Compilation Time chapter
  • Removed references to Timing Closure Floorplan
  • Moved Smart Compilation Setting and Early Timing Estimation sections to new Reducing Compilation Time chapter
  • Added Other Optimization Resources section
  • Removed outdated information
  • Changed references to DSE chapter to Help links
  • Linked to Help where appropriate
  • Removed Referenced Documents section

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