1. Design Optimization Overview 2. Optimizing the Design Netlist 3. Timing Closure and Optimization 4. Area Optimization 5. Analyzing and Optimizing the Design Floorplan 6. Netlist Optimizations and Physical Synthesis 7. Engineering Change Orders with the Chip Planner A. Intel® Quartus® Prime Standard Edition User Guides
2.1. When to Use the Netlist Viewers: Analyzing Design Problems 2.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers 2.3. RTL Viewer Overview 2.4. State Machine Viewer Overview 2.5. Technology Map Viewer Overview 2.6. Netlist Viewer User Interface 2.7. Schematic View 2.8. State Machine Viewer 2.9. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows 2.10. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows 2.11. Viewing a Timing Path 2.12. Optimizing the Design Netlist Revision History
2.7.1. Display Schematics in Multiple Tabbed View 2.7.2. Schematic Symbols 2.7.3. Select Items in the Schematic View 2.7.4. Shortcut Menu Commands in the Schematic View 2.7.5. Filtering in the Schematic View 2.7.6. View Contents of Nodes in the Schematic View 2.7.7. Moving Nodes in the Schematic View 2.7.8. View LUT Representations in the Technology Map Viewer 2.7.9. Zoom Controls 2.7.10. Navigating with the Bird's Eye View 2.7.11. Partition the Schematic into Pages 2.7.12. Follow Nets Across Schematic Pages
3.1. Optimize Multi Corner Timing 3.2. Critical Paths 3.3. Design Evaluation for Timing Closure 3.4. Design Analysis 3.5. Timing Optimization 3.6. Periphery to Core Register Placement and Routing Optimization 3.77.7. Scripting Support3.77.7. Scripting Support 3.8. Timing Closure and Optimization Revision History
126.96.36.199. Displaying Path Reports with the Timing Analyzer 188.8.131.52. Tips for Analyzing Failing Paths 184.108.40.206. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 220.127.116.11. Tips for Analyzing Paths from/to the Source and Destination of Critical Path 18.104.22.168. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 22.214.171.124. Global Routing Resources
3.5.1. Displaying Timing Closure Recommendations for Failing Paths 3.5.2. Timing Optimization Advisor 3.5.3. Optional Fitter Settings 3.5.4. I/O Timing Optimization Techniques 3.5.5. Register-to-Register Timing Optimization Techniques 3.5.6. Logic Lock (Standard) Assignments 3.5.7. Location Assignments 3.5.8. Metastability Analysis and Optimization Techniques
126.96.36.199. Optimize IOC Register Placement for Timing Logic Option 188.8.131.52. Fast Input, Output, and Output Enable Registers 184.108.40.206. Programmable Delays 220.127.116.11. Use PLLs to Shift Clock Edges 18.104.22.168. Use Fast Regional Clock Networks and Regional Clocks Networks 22.214.171.124. Spine Clock Limitations 126.96.36.199. Change How Hold Times are Optimized for Devices
188.8.131.52. Optimize Source Code 184.108.40.206. Improving Register-to-Register Timing 220.127.116.11. Physical Synthesis Optimizations 18.104.22.168. Turn Off Extra-Effort Power Optimization Settings 22.214.171.124. Optimize Synthesis for Speed, Not Area 126.96.36.199. Flatten the Hierarchy During Synthesis 188.8.131.52. Set the Synthesis Effort to High 184.108.40.206. Change State Machine Encoding 220.127.116.11. Duplicate Logic for Fan-Out Control 18.104.22.168. Prevent Shift Register Inference 22.214.171.124. Use Other Synthesis Options Available in Your Synthesis Tool 126.96.36.199. Fitter Seed 188.8.131.52. Set Maximum Router Timing Optimization Level
184.108.40.206. Guideline: Optimize Source Code 220.127.116.11. Guideline: Optimize Synthesis for Area, Not Speed 18.104.22.168. Guideline: Restructure Multiplexers 22.214.171.124. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 126.96.36.199. Guideline: Use Register Packing 188.8.131.52. Guideline: Remove Fitter Constraints 184.108.40.206. Guideline: Flatten the Hierarchy During Synthesis 220.127.116.11. Guideline: Re-target Memory Blocks 18.104.22.168. Guideline: Use Physical Synthesis Options to Reduce Area 22.214.171.124. Guideline: Retarget or Balance DSP Blocks 126.96.36.199. Guideline: Use a Larger Device
188.8.131.52. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 184.108.40.206. Guideline: Set Fitter Aggressive Routability Optimizations to Always 220.127.116.11. Guideline: Increase Router Effort Multiplier 18.104.22.168. Guideline: Remove Fitter Constraints 22.214.171.124. Guideline: Optimize Synthesis for Area, Not Speed 126.96.36.199. Guideline: Optimize Source Code 188.8.131.52. Guideline: Use a Larger Device
5.1.1. Starting the Chip Planner 5.1.2. Chip Planner GUI Components 5.1.3. Viewing Architecture-Specific Design Information 5.1.4. Viewing Available Clock Networks in the Device 5.1.5. Viewing Routing Congestion 5.1.6. Viewing I/O Banks 5.1.7. Viewing High-Speed Serial Interfaces (HSSI) 5.1.8. Viewing the Source and Destination of Placed Nodes 5.1.9. Viewing Fan-In and Fan-Out Connections of Placed Resources 5.1.10. Generating Immediate Fan-In and Fan-Out Connections 5.1.11. Exploring Paths in the Chip Planner 5.1.12. Viewing Assignments in the Chip Planner 5.1.13. Viewing High-Speed and Low-Power Tiles in the Chip Planner 5.1.14. Viewing Design Partition Placement
5.2.1. Attributes of a Logic Lock (Standard) Region 5.2.2. Creating Logic Lock (Standard) Regions 5.2.3. Customizing the Shape of Logic Lock Regions 5.2.4. Placing Logic Lock (Standard) Regions 5.2.5. Placing Device Resources into Logic Lock (Standard) Regions 5.2.6. Hierarchical (Parent and Child) Logic Lock (Standard) Regions 5.2.7. Additional Intel® Quartus® Prime Logic Lock (Standard) Design Features 5.2.8. Logic Lock (Standard) Regions Window
184.108.40.206. Creating Logic Lock (Standard) Regions with the Chip Planner 220.127.116.11. Creating Logic Lock (Standard) Regions with the Project Navigator 18.104.22.168. Creating Logic Lock (Standard) Regions with the Logic Lock (Standard) Regions Window 22.214.171.124. Defining Routing Regions 126.96.36.199. Noncontiguous Logic Lock (Standard) Regions 188.8.131.52. Considerations on Using Auto Sized Regions
5.4.1. Initializing and Uninitializing a Logic Lock (Standard) Region 5.4.2. Creating or Modifying Logic Lock (Standard) Regions 5.4.3. Obtaining Logic Lock (Standard) Region Properties 5.4.4. Assigning Logic Lock (Standard) Region Content 5.4.5. Save a Node-Level Netlist for the Entire Design into a Persistent Source File 5.4.6. Setting Logic Lock (Standard) Assignment Priority 5.4.7. Assigning Virtual Pins with a Tcl command
7.1. Engineering Change Orders 7.2. ECO Design Flow 7.3. The Chip Planner Overview 7.4. Performing ECOs with the Chip Planner (Floorplan View) 7.5. Performing ECOs in the Resource Property Editor 7.6. Change Manager 3.77.7. Scripting Support3.77.7. Scripting Support 7.8. Common ECO Applications 7.9. Post ECO Steps 7.10. Engineering Change Orders with the Chip Planner Revision History
184.108.40.206. Tips for Analyzing Failing Clock Paths that Cross Clock Domains
When analyzing clock path failures:
- Check whether these paths cross two clock domains.
In paths that cross two clock domains, the From Clock and To Clock in the timing analysis report are different.Figure 27. Different Value in From Clock and To Clock Field
- Check if the design contains paths that involve a different clock in the middle of the path, even if the source and destination register clock are the same.
- Check whether failing paths between these clock domains need to be analyzed synchronously.
Set failing paths that are not to be analyzed synchronously as false paths.
- When you run report_timing on a design, the report shows the launch clock and latch clock for each failing path. Check whether the relationship between the launch clock and latch clock is realistic and what you expect from your knowledge of the design
For example, the path can start at a rising edge and end at a falling edge, which reduces the setup relationship by one half clock cycle.
- Review the clock skew that appears in the Timing Report:
A large skew may indicate a problem in the design, such as a gated clock, or a problem in the physical layout (for example, a clock using local routing instead of dedicated clock routing). When you have made sure the paths are analyzed synchronously and that there is no large skew on the path, and that the constraints are correct, you can analyze the data path. These steps help you fine tune your constraints for paths across clock domains to ensure you get an accurate timing report.
- Check if the PLL phase shift is reducing the setup requirement.
You might adjust this by using PLL parameters and settings.
- Ignore paths that cross clock domains for logic protected with synchronization logic (for example, FIFOs or double-data synchronization registers), even if the clocks are related.
- Set false path constraints on all unnecessary paths:
Attempting to optimize unnecessary paths can prevent the Fitter from meeting the timing requirements on timing paths that are critical to the design.
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