1.3. Trade-Offs and Limitations
|Resource usage and critical path timing.||Certain techniques (such as logic duplication) can improve timing performance at the cost of increased area.|
|Power requirements can result in area and timing trade-offs.||For example, reducing the number of available high-speed tiles, or attempting to shorten high-power nets at the expense of critical path nets.|
|System cost and time-to-market considerations can affect the choice of device.||For example, a device with a higher speed grade or more clock networks can facilitate timing closure at the expense of higher power consumption and system cost.|
Finally, constrains that are too severe limit design feasibility as far as no possible solution for the selected device. If the Fitter cannot resolve a design due to resource limitations, timing constraints, or power constraints, consider rewriting parts of the HDL code.
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