Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

5.5. Analyzing and Optimizing the Design Floorplan Revision History

The following revision history applies to this chapter:

Table 20.  Document Revision History
Document Version Intel® Quartus® Prime Version Changes
2018.09.24 18.1.0
  • Initial release in Intel Quartus Prime Standard Edition User Guide.
  • Renamed topic: Generating Fan-In and Fan-Out Connections to Viewing Fan-In and Fan-Out Connections of Placed Resources.
2018.05.07 18.0.0
  • Added recommendations for using iterative methods for floorplanning.
2017.11.06 17.1.0
  • Changed instances of LogicLock to Logic Lock (Standard).
2017.05.08 17.0.0
  • Chapter reorganization and content update.
  • Added figures: Clock Regions, Creating a Hole in a LogicLock Region, Noncontiguous LogicLock Region, Routing Regions, Logic Placed Outside of an Empty Region.
  • Moved topic: Viewing Critical Paths to Timing Closure and Optimization chapter and renamed to Critical Paths.
  • Renamed topic: Creating Non-Rectangular LogicLock Plus Regions to Merging LogicLock Plus Regions.
  • Renamed topic: Chip Planner Overview to Design Floorplan Analysis in the Chip Planner.
  • Renamed chapter from Analyzing and Optimizing the Design Floorplan with the Chip Planner to Analyzing and Optimizing the Design Floorplan.
2015.11.02 15.1.0
  • Changed instances of Quartus II to Quartus Prime.
2015.05.04 15.0.0 Added information about color coding of LogicLock regions.
2014.12.15 14.1.0 Updated description of Virtual Pins assignment to clarify that assigned input is not available.
June 2014 14.0.0 Updated format
November 2013 13.1.0 Removed HardCopy device information.
May 2013 13.0.0 Updated “Viewing Routing Congestion” section

Updated references to Quartus UI controls for the Chip Planner

June 2012 12.0.0 Removed survey link.
November 2011 11.0.1 Template update.
May 2011 11.0.0
  • Updated for the 11.0 release.

    Edited “LogicLock Regions”

    Updated “Viewing Routing Congestion”

    Updated “Locate History”

    Updated Figures 15-4, 15-9, 15-10, and 15-13

    Added Figure 15-6

December 2010 10.1.0
  • Updated for the 10.1 release.
July 2010 10.0.0
  • Updated device support information
  • Removed references to Timing Closure Floorplan; removed “Design Analysis Using the Timing Closure Floorplan” section
  • Added links to online Help topics
  • Added “Using LogicLock Regions with the Design Partition Planner” section
  • Updated “Viewing Critical Paths” section
  • Updated several graphics
  • Updated format of Document revision History table
November 2009 9.1.0
  • Updated supported device information throughout
  • Removed deprecated sections related to the Timing Closure Floorplan for older device families. (For information on using the Timing Closure Floorplan with older device families, refer to previous versions of the Quartus Prime Handbook, available in the Documentation Archive.)
  • Updated “Creating Nonrectangular LogicLock Regions” section
  • Added “Selected Elements Window” section
  • Updated table 12-1
May 2008 8.0.0
  • Updated the following sections:

    “Chip Planner Tasks and Layers”

    “LogicLock Regions”

    “Back-Annotating LogicLock Regions”

    “LogicLock Regions in the Timing Closure Floorplan”

  • Added the following sections:

    “Reserve LogicLock Region”

    “Creating Nonrectangular LogicLock Regions”

    “Viewing Available Clock Networks in the Device”

  • Updated Table 10–1
  • Removed the following sections:

    Reserve LogicLock Region Design Analysis Using the Timing Closure Floorplan