Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents Optimize IOC Register Placement for Timing Logic Option

This option moves registers into I/O elements to meet tSU or tCO assignments, duplicating the register if necessary (as in the case in which a register fans out to multiple output locations). This option is turned on by default and is a global setting.
Note: The option does not apply to series devices because they do not contain I/O registers.
The Optimize IOC Register Placement for Timing logic option affects only pins that have a tSU or tCO requirement. Using the I/O register is possible only if the register directly feeds a pin or is fed directly by a pin. Therefore, this logic option does not affect registers with any of the following characteristics:
Note: To optimize registers with these characteristics, use other Intel® Quartus® Prime Fitter optimizations.
  • Have combinational logic between the register and the pin
  • Are part of a carry or cascade chain
  • Have an overriding location assignment
  • Use the asynchronous load port and the value is not 1 (in device families where the port is available)