Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

7.5.3. FPGA I/O Elements

Altera FPGAs that have high-performance I/O elements, including up to six registers, are equipped with support for a number of I/O standards that allow you to run your design at peak speeds. Use the Resource Property Editor to view, change connectivity, and edit the properties of the I/O elements. Use the Chip Planner (Floorplan view) to change placement, delete, and create new I/O elements.

For a detailed description of the device I/O elements, refer to the applicable device handbook.

You can change the following I/O properties:

  • Delay chain
  • Bus hold
  • Weak pull up
  • Slow slew rate
  • I/O standard
  • Current strength
  • Extend OE disable
  • PCI I/O
  • Register reset mode
  • Register synchronous reset mode
  • Register power up
  • Register mode