Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

7.2. ECO Design Flow

For iterative verification cycles, implementing small design changes at the netlist level can be faster than making an RTL code change. As such, making ECO changes are especially helpful when you debug the design on silicon and require a fast turnaround time to generate a programming file for debugging the design.
Note: The Intel® Quartus® Prime Standard Edition ECO feature does not support Intel® Arria® 10 devices.
The figure shows the design flow for making ECOs.
Figure 52. Design Flow to Support ECOs


A typical ECO application occurs when you uncover a problem on the board and isolate the problem to the appropriate nodes or I/O cells on the device. You must be able to correct the functionality quickly and generate a new programming file. By making small changes with the Chip Planner, you can modify the post-place-and-route netlist directly without having to perform synthesis and logic mapping, thus decreasing the turnaround time for programming file generation during the verification cycle. If the change corrects the problem, no modification of the HDL source code is necessary. You can use the Chip Planner to perform the following ECO-related changes to your design:

  • Document the changes made with the Change Manager
  • Easily recreate the steps taken to produce design changes
  • Generate EDA simulation netlists for design verification
Note: For more complex changes that require HDL source code modifications, the incremental compilation feature can help reduce recompilation time.

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