188.8.131.52. Guideline: Optimize Synthesis for Area, Not Speed
First, ensure that the device and timing constraints are set correctly in the synthesis tool. Particularly when area utilization of the design is a concern, ensure that you do not over-constrain the timing requirements for the design. Synthesis tools try to meet the specified requirements, which can result in higher device resource usage if the constraints are too aggressive.
If resource utilization is an important concern, you can optimize for area instead of speed.
- If you are using Intel® Quartus® Prime integrated synthesis, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) and select Balanced or Area for the Optimization Technique.
- If you want to reduce area for specific modules in the design using the Area or Speed setting while leaving the default Optimization Technique setting at Balanced, use the Assignment Editor.
- You can also turn on the Speed Optimization Technique for Clock Domains logic option to optimize for speed all combinational logic in or between the specified clock domains.
- In some synthesis tools, not specifying an fMAX requirement can result in less resource utilization.
Optimizing for area or speed can affect the register-to-register timing performance.
The Intel® Quartus® Prime software provides additional attributes and options that can help improve the quality of the synthesis results.
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