Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

2.3.1. Maximizing Readability in RTL Viewer

While displaying a design, the RTL Viewer optimizes the netlist to maximize readability:

  • Removes logic with no fan-out (unconnected output) or fan-in (unconnected inputs) from the display.
  • Hides default connections such as VCC and GND.
  • Groups pins, nets, wires, module ports, and certain logic into buses where appropriate.
  • Groups constant bus connections.
  • Displays values in hexadecimal format.
  • Converts NOT gates into bubble inversion symbols in the schematic.
  • Merges chains of equivalent combinational gates into a single gate; for example, a 2-input AND gate feeding a 2-input AND gate is converted to a single 3-input AND gate.
  • Converts state machine logic into a state diagram, state transition table, and state encoding table, which appear in the State Machine Viewer.

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