Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents Evaluate Other Reports and Adjust Settings Accordingly

Difficulty Packing Design

In the Fitter Resource Section, under the Resource Usage Summary, review the Difficulty Packing Design report. The Difficulty Packing Design report details the effort level (low, medium, or high) of the Fitter to fit the design into the device, partition, and Logic Lock (Standard) region.

As the effort level of Difficulty Packing Design increases, timing closure gets harder. Going from medium to high can result in significant drop in performance or increase in compile time. Consider reducing logic to reduce packing difficulty.

Review Ignored Assignments

The Compilation Report includes details of any assignments ignored by the Fitter. Assignments typically get ignored if design names change, but assignments are not updated. Make sure any intended assignments are not being ignored.

Review Non-Default Settings

The reports from Synthesis and Fitter show non-default settings used in a compilation. Review the non-default settings to ensure the design benefits from the change.

Review Floorplan

Use the Chip Planner for reviewing placement. You can use the Chip Planner to locate hierarchical entities, using colors for each located entity in the floorplan. Look for logic that seems out of place, based on where you expect it to be

For example, logic that interfaces with I/Os should be close to the I/Os, and logic that interfaces with an IP or memory should be close to the IP or memory.

Figure 20. Floorplan with Color-Coded Entities

The following notes describe how you can use the visualization in Floorplan with Color-Coded Entities to check timing paths:

  • The green block is spread apart. Check to see if those paths are failing timing, and if so, what connects to that module that could affect placement.
  • The blue and aqua blocks are spread out and mixed together. Check if connections between the two modules contribute to this.
  • The pink logic at the bottom must interface with I/Os at the bottom edge. Check fan-in and fan-out of a highlighted module by using the buttons on the task bar.

    Look for signals that go a long way across the chip and see if they are contributing to timing failures.

  • Check global signal usage for signals that affect logic placement, and verify if the Fitter placed logic feeding a global buffer close to the buffer and away from related logic. Use settings like high fan-out on non-global resource to pull logic together.
  • Check for routing congestion. The Fitter spreads out logic in highly congested areas, making the design harder to route.

Evaluate Placement and Routing

Review duration of parts of compile time in Fitter messages. If routing takes much more time than placement, then meeting timing may be more difficult than the placer predicted.

Adjust Placement Effort

You can increase the Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Placement Effort Multiplier value to spend additional compilation time and effort in Place stage of the Fitter.

Adjust the multiplier after reviewing and optimizing other settings and RTL. Try an increased value, up to 4, and reset to default if performance or compile time does not improve.

Figure 21. Placement Effort Multiplier

Adjust Fitter Effort

Fitter Optimization mode settings allow you to specify whether the Compiler focuses optimization efforts for performance, resource utilization, power, or compile times.

By default, the Fitter Optimization mode is set to Balanced (Normal flow), which reduces Fitter effort once timing requirements are met. You can optionally select another Optimization mode to target performance, power, or resource usage.

To increase Fitter effort further, you can also enable the Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Fitter Effort option. The default Auto Fit setting reduces Fitter effort once timing requirements are met. Standard Fit (highest effort) setting uses maximum effort regardless of the design's requirements, leading to higher compilation time and more timing margin.

Figure 22. Fitter Effort

Review Timing Constraints

Ensure that clocks are constrained with the correct frequency requirements. Using the derive_pll_clocks assignment keeps generated clock settings updated. Timing Analyzer can be useful in reviewing SDC constraints. For example, under Diagnostic in the Task panel, the Report Ignored Constraints report shows any incorrect names in the design, most commonly caused by changes in the design hierarchy. Use the Report Unconstrained Paths report to locate unconstrained paths. Add constraints as necessary so that the design can be optimized.