7. Engineering Change Orders with the Chip Planner
The Chip Planner supports ECOs by allowing quick and efficient changes to your logic late in the design cycle for supported devices. The Chip Planner provides a visual display of your post-place-and-route design mapped to the device architecture of your chosen FPGA and allows you to create, move, and delete logic cells and I/O atoms.
In addition to making ECOs, the Chip Planner allows you to perform detailed analysis on routing congestion, relative resource usage, logic placement, Logic Lock (Standard) regions, fan-ins and fan-outs, paths between registers, and delay estimates for paths.
ECOs directly apply to atoms in the supported target device. As such, performing an ECO relies on your understanding of the device architecture of the target device.
Engineering Change Orders
ECO Design Flow
The Chip Planner Overview
Performing ECOs with the Chip Planner (Floorplan View)
Performing ECOs in the Resource Property Editor
Common ECO Applications
Post ECO Steps
Engineering Change Orders with the Chip Planner Revision History
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