Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Document Table of Contents

7.1.3. Verification

After you make a design change, you can verify the impact on your design. To verify that your changes do not violate timing requirements, perform static timing analysis with the Intel® Quartus® Prime Timing Analyzer after you check and save your netlist changes in the Chip Planner.

Additionally, you can perform a gate-level or timing simulation of the ECO-modified design with the post-place-and-route netlist generated by the Intel® Quartus® Prime software.