126.96.36.199. Guideline: Re-target Memory Blocks
For memory blocks created with the Parameter Editor, edit the RAM block type to target a new memory block size.
The Compiler can also infer ROM and RAM memory blocks from the HDL code, and the synthesis engine can place large shift registers into memory blocks by inferring the Shift register (RAM-based) IP core. When you turn off this inference in the synthesis tool, the synthesis engine places the memory or shift registers in logic instead of memory blocks. Also, turning off this inference prevents registers from being moved into RAM, improving timing performance,
Depending on the synthesis tool, you can also set the RAM block type for inferred memory blocks. In Intel® Quartus® Prime synthesis, set the ramstyle attribute to the desired memory type for the inferred RAM blocks. Alternatively, set the option to logic to implement the memory block in standard logic instead of a memory block.
Consider the Resource Utilization by Entity report in the report file and determine whether there is an unusually high register count in any of the modules. Some coding styles prevent the Intel® Quartus® Prime software from inferring RAM blocks from the source code because of the blocks’ architectural implementation, forcing the software to implement the logic in flip-flops. For example, an asynchronous reset on a register bank might make the register bank incompatible with the RAM blocks in the device architecture, so Compiler implements the register bank in flip-flops. It is often possible to move a large register bank into RAM by slight modification of associated logic.
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