Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

ID 683230
Date 11/12/2018
Public
Document Table of Contents

3.7.3. Register-to-Register Timing Optimization Techniques

The table lists the .qsf file variable name and applicable values for the settings described in Register-to-Register Timing Optimization Techniques.

Table 15.  Register-to-Register Timing Optimization Settings     
Setting Name .qsf File Variable Name Values Type
Perform WYSIWYG Primitive Resynthesis ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON, OFF Global, Instance
Perform Physical Synthesis for Combinational Logic (no Intel® Arria® 10 support) PHYSICAL_SYNTHESIS_COMBO_LOGIC ON, OFF Global, Instance
Perform Register Duplication (no Intel® Arria® 10 support) PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON, OFF Global, Instance
Perform Register Retiming (no Intel® Arria® 10 support) PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON, OFF Global, Instance
Perform Automatic Asynchronous Signal Pipelining (no Intel® Arria® 10 support) PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON, OFF Global, Instance
Physical Synthesis Effort (no Intel® Arria® 10 support) PHYSICAL_SYNTHESIS_EFFORT NORMAL, EXTRA, FAST Global
Fitter Seed SEED <integer> Global
Maximum Fan-Out MAX_FANOUT <integer> Instance
Manual Logic Duplication DUPLICATE_ATOM <node name> Instance
Optimize Power during Synthesis OPTIMIZE_POWER_DURING_SYNTHESIS NORMAL, OFF 
EXTRA_EFFORT Global
Optimize Power during Fitting OPTIMIZE_POWER_DURING_FITTING NORMAL, OFF 
EXTRA_EFFORT Global

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