Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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2.4.1. Transmitter Blocks in Intel® Stratix® 10 Devices

The dedicated circuitry consists of a true differential buffer, a serializer, and I/O PLLs that you can share between the transmitter and receiver. The serializer takes up to 10-bit wide parallel data from the FPGA fabric and clocks the data into the load registers. Then, the serializer serializes the data using shift registers that are clocked by the I/O PLL. After serializing the data, the serializer sends the data to the differential buffer. The MSB of the parallel data is transmitted first.

Note: The PLL that drives the LVDS SERDES channel must operate in integer PLL mode. You do not need a PLL if you bypass the serializer.
Figure 6. LVDS TransmitterThis figure shows a block diagram of the transmitter. In SDR and DDR modes, the data width is 1 and 2 bits, respectively.


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