5.1.2. LVDS SERDES Intel® FPGA IP PLL Settings
|Use external PLL||
Turn on to use an external PLL:
This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration.
Note: If you want to place combined LVDS transmitters and receivers in the same I/O bank using two LVDS SERDES IP core instances, you must turn on this option. You can also place combined transmitters and receivers in the same I/O bank by turning on the Duplex Feature option in the General Settings tab. If you turn on Duplex Feature, the Use external PLL option is disabled.
|Desired inclock frequency||—||
Specifies the inclock frequency in MHz.
|Actual inclock frequency||—||
Displays the closest inclock frequency to the desired frequency that can source the interface.
|FPGA/PLL speed grade||—||
Displays the FPGA/PLL speed grade, which determines the operation range of the PLL.
|Enable pll_areset port||
Turn on to expose the pll_areset port. You can use the pll_areset signal to reset the entire LVDS interface.
This setting is enabled if if you turn on Use external PLL.
|Core clock resource type||—||
Specifies onto which clock network the IP core exports an internally generated coreclock.
Note: This feature will be supported in a future version of the Intel® Quartus® Prime software. Currently, use QSF assignments to manually specify this parameter.
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