Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

3.1.7. LVDS Interface with External PLL Mode

The LVDS SERDES IP parameter editor provides an option to implement the LVDS interface with the Use External PLL option. With this option turned on you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings.

If you enable the Use External PLL option with the LVDS SERDES IP core transmitter and receiver, the following signals are required from the IOPLL Intel® FPGA IP:

  • Serial clock (fast clock) input to the SERDES of the LVDS SERDES IP transmitter and receiver
  • Load enable to the SERDES of the LVDS SERDES IP transmitter and receiver
  • Parallel clock (core clock) used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
  • Asynchronous PLL reset port of the LVDS SERDES IP receiver
  • PLL VCO signal for the DPA and soft-CDR modes of the LVDS SERDES IP receiver

The Clock Resource Summary tab in the LVDS SERDES IP parameter editor provides the details for the signals in the preceding list.

You must instantiate an IOPLL IP to generate the various clocks and load enable signals. Configure these settings in the IOPLL IP parameter editor:

  • In the Settings tab, specify the LVDS External PLL settings.
  • In the PLL tab:
    • Set the Output Clocks settings.
    • Select the Compensation Mode according to the following table.
Table 9.  Compensation Mode Setting to Generate IOPLL IPWhen you generate the IOPLL IP, use the PLL compensation mode in this table for the corresponding LVDS functional mode.
LVDS Functional Mode IOPLL IP Compensation Mode
TX, RX DPA, RX Soft-CDR direct
RX non-DPA lvds
Note: If you are using an external PLL for a wide transmitter interface that spans multiple I/O banks, only the second pair of clocks (indexed by "[1]") from the external PLL is valid.