3.1.7. LVDS Interface with External PLL Mode
If you enable the Use External PLL option with the LVDS SERDES IP core transmitter and receiver, the following signals are required from the IOPLL Intel® FPGA IP:
- Serial clock (fast clock) input to the SERDES of the LVDS SERDES IP transmitter and receiver
- Load enable to the SERDES of the LVDS SERDES IP transmitter and receiver
- Parallel clock (core clock) used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
- Asynchronous PLL reset port of the LVDS SERDES IP receiver
- PLL VCO signal for the DPA and soft-CDR modes of the LVDS SERDES IP receiver
The Clock Resource Summary tab in the LVDS SERDES IP parameter editor provides the details for the signals in the preceding list.
You must instantiate an IOPLL IP to generate the various clocks and load enable signals. Configure these settings in the IOPLL IP parameter editor:
- In the Settings tab, specify the LVDS External PLL settings.
- In the PLL tab:
- Set the Output Clocks settings.
- Select the Compensation Mode according to the following table.
|LVDS Functional Mode||IOPLL IP Compensation Mode|
|TX, RX DPA, RX Soft-CDR||direct|
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