Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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5.3. Comparison of LVDS SERDES Intel® FPGA IP with Stratix® V SERDES

The LVDS SERDES IP core has similar features to the Stratix® V SERDES. The key differences are the clock network and the ubiquitous RX and TX resource in LVDS I/O banks.
Table 35.   Intel® Stratix® 10 and Stratix® V Devices Feature Comparison
Features Intel® Stratix® 10 Devices Stratix® V Devices
Operation Frequency Range 150 MHz - 1.6 GHz
Serialization/Deserialization Factors 3 to 10
Regular DPA and non-DPA mode Supported
Clock Forwarding for Soft-CDR Supported
RX Resource Every I/O pair

(Every two I/O pairs for CDR)

Every two I/O pairs on every side without HSSI transceivers
TX Resource Every I/O pair Every two I/O pairs every side without HSSI transceivers
PLL Resource TX channels can span three adjacent banks, driven by the IOPLL in the middle bank.

RX channels are driven by the IOPLL in the same bank.

RX and TX channels placed on one edge can be driven by the corner or center PLL.
Number of DPA Clock Phase 8
I/O Standard True LVDS True LVDS, pseudo-differential output

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