Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
Document Table of Contents

4.1.4.1. Serializer

The serializer consists of two sets of registers.

The first set of registers captures the parallel data from the core using the LVDS fast clock. The load_enable clock is provided alongside the LVDS fast clock, to enable these capture registers once in each coreclock period.

After the data is captured, it is loaded into a shift register that shifts the LSB towards the MSB at one bit per fast clock cycle. The MSB of the shift register feeds the LVDS output buffer. Therefore, higher order bits precede lower order bits in the output bitstream.

Figure 34.  LVDS x8 Serializer WaveformThis figure shows the waveform specific to serialization factor of eight.


Table 18.  LVDS Serializer Signals
Signal Description
tx_in[7:0]

Data for serialization

(Supported serialization factors: 3–10)

fast_clock Clock for the transmitter
load_enable Enable signal for serialization
lvdsout LVDS output data stream from the LVDS SERDES IP core channel

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