The first set of registers captures the parallel data from the core using the LVDS fast clock. The load_enable clock is provided alongside the LVDS fast clock, to enable these capture registers once in each coreclock period.
After the data is captured, it is loaded into a shift register that shifts the LSB towards the MSB at one bit per fast clock cycle. The MSB of the shift register feeds the LVDS output buffer. Therefore, higher order bits precede lower order bits in the output bitstream.
Data for serialization
(Supported serialization factors: 3–10)
|Clock for the transmitter
|Enable signal for serialization
|LVDS output data stream from the LVDS SERDES IP core channel