Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

3.1.7.1. IOPLL IP Signal Interface with LVDS SERDES IP

Table 10.  Signal Interface between IOPLL and LVDS SERDES IPs This table lists the signal interface between the output ports of the IOPLL IP and the input ports of the LVDS SERDES IP transmitter or receiver. The required signal interfaces differ if you turn on the Clock Phase Alignment (CPA) feature of the LVDS SERDES IP.
From the IOPLL IP To the LVDS SERDES IP Transmitter or Receiver
Without CPA With CPA
lvds_clk[0] (serial clock output signal)
  • Configure this signal using outclk0 in the PLL.
  • Select Enable LVDS_CLK/LOADEN 0 or Enable LVDS_CLK/LOADEN 0 & 1 option for the Access to PLL LVDS_CLK/LOADEN output port setting. In most cases, select Enable LVDS_CLK/LOADEN 0.

The serial clock output can only drive ext_fclk on the LVDS SERDES IP transmitter and receiver. This clock cannot drive the core logic.

ext_fclk (serial clock input to the transmitter or receiver)

ext_fclk (serial clock input to the transmitter or receiver)

loaden[0] (load enable output)

  • Configure this signal using outclk1 in the PLL.
  • Select Enable LVDS_CLK/LOADEN 0 or Enable LVDS_CLK/LOADEN 0 & 1 option for the Access to PLL LVDS_CLK/LOADEN output port setting. In most cases, select Enable LVDS_CLK/LOADEN 0.

ext_loaden (load enable to the transmitter or receiver)

This signal is not required for LVDS receiver in soft-CDR mode.

ext_loaden (load enable to the transmitter or receiver)

This signal is not required for LVDS receiver in soft-CDR mode.

outclk4 (parallel clock output)

This clock is not required if you turn on Use the CPA block for improved periphery-core timing.

ext_coreclock (parallel core clock)

locked

ext_pll_locked

reset

pll_areset (asynchronous PLL reset port)

pll_areset (asynchronous PLL reset port)

phout[7:0]

  • This signal is required if ext_vcoph[7:0] is required.

  • Configure this signal by turning on Specify VCO frequency in the PLL and specifying the VCO frequency value.
  • Turn on Enable access to PLL DPA output port.

ext_vcoph[7:0]

This signal is required only for LVDS receiver in DPA or soft-CDR mode.

ext_vcoph[7:0]

This signal is required for all transmitter or receiver modes.

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