Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

4.4.4. LVDS SERDES IP Dynamic Phase Shift Design Example

The dynamic phase shift design example provides you live control over the PLL clock shifts in an LVDS design through a flexible TCL script interface.
Note: The dynamic phase shift design example does not support the duplex mode. If your LVDS SERDES IP uses the Duplex Feature mode, ignore the ed_synth_dps.qsys file generated by the Generate Example Design command.

You can use this example in LVDS-specific applications such as debugging non-DPA receiver capture where you can repeatedly shift the capture clock to find the best operational phase shift.

You can also use the design example as a general example of using the In-System Sources and Probes feature with Signal Tap to interface with your hardware through TCL scripting. This method allows you to use manual switches to test a board without being physically present.

The dynamic phase shift design example uses LVDS SERDES IP parameter settings and connects the IP to an external PLL. The PLL has an exposed dynamic phase shift interface that connects to in-system sources and probes. This connection allows you to control the PLL using the In-System Sources and Probes editor or the provided TCL script in conjunction with Signal Tap.

A part of the LVDS SERDES IP in the design example is also connected to the in-system sources and probes. The provided TCL script shows an example of how you can shift a selected PLL clock and also provides you some utility functions. You can use this example script as a start towards accomplishing the testing function that you want.

Figure 41.  LVDS SERDES IP Dynamic Phase Shift

Generating and Using the Design Example

To generate the combined dynamic phase shift design example from the source files, run the following command in the design example directory:

quartus_sh -t make_qii_design.tcl -system ed_synth_dps

The TCL script creates a qii_ed_synth_dps directory that contains the ed_synth_dps.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.

To use the provided TCL script to control the in-system sources and probes, run the following command:

quartus_stp -t dps_issp.tcl qii_ed_synth_dps/ed_synth_dps
Note: For the control to work, you must first program the FPGA.

For more information about make_qii_design.tcl arguments, run the following command:

quartus_sh -t make_qii_design.tcl -help

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