Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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5.1.3. LVDS SERDES Intel® FPGA IP Receiver Settings

The parameter options in the Receiver Settings tab are available if you select the RX Non-DPA, RX DPA-FIFO, or RX Soft-CDR functional mode in the General Settings tab.
Table 27.  Receiver Settings Tab—Bitslip Settings
Parameter Value Description
Enable bitslip mode
  • On
  • Off

Turn on to add a bit slip block to the receiver data path and expose the rx_bitslip_ctrl port (one input per channel).

Every assertion of the rx_bitslip_ctrl signal adds one bit of serial latency to the data path of the specified channel.

Enable rx_bitslip_reset port
  • On
  • Off

Turn on to expose the rx_bitslip_reset port (one input per channel) that you can use to reset the bit slip.

Enable rx_bitslip_max port
  • On
  • Off

Turn on to expose the rx_bitslip_max port (one output per channel).

When asserted, the next rising edge of rx_bitslip_ctrl resets the latency of the bit slip to zero.

Bitslip rollover value Deserialization factor

Specifies the maximum latency that the bit slip can inject.

When the bit slip reaches the specified value, it rolls over and the rx_bitslip_max signal asserts.

The rollover value is set automatically to the deserialization factor.

Table 28.  Receiver Settings Tab—DPA Settings
Parameter Value Description
Enable rx_dpa_reset port
  • On
  • Off

Turn on to expose the rx_dpa_reset port that you can use to reset the DPA logic of each channel independently.

(Formerly known as rx_reset.)

Enable rx_fifo_reset port
  • On
  • Off

Turn on to use your logic to drive the rx_fifo_reset port to reset the DPA-FIFO block.

Enable rx_dpa_hold port
  • On
  • Off

Turn on to expose the rx_dpa_hold input port (one input per channel).

If set high, the DPA logic in the corresponding channel does not switch sampling phases.

(Formerly known as rx_dpll_hold.)

Enable DPA loss of lock on one change
  • On
  • Off
  • On—the IP drives the rx_dpa_locked signal low when the DPA changes phase selection from the initially locked position. When the DPA changes the phase selection back to the initial locked position, the IP drives the rx_dpa_locked signal high.
  • Off—the IP drives the rx_dpa_locked signal low when the DPA moves two phases in the same direction away from the initial locked position. When the DPA changes the phase selection to be within one phase or same phase as the initial locked position, the IP drives the rx_dpa_locked signal high.

Deassertion of rx_dpa_locked does not indicate that the data is invalid. Instead, the deassertion indicates that the DPA has changed phase taps to track variations between the inclock and rx_in data.

Intel recommends that you use data checkers to verify data accuracy.

Enable DPA alignment only to rising edges of data
  • On
  • Off
  • On—DPA logic counts only the rising edges of the incoming serial data
  • Off—DPA logic counts the rising and falling edges
Note: Intel recommends that you use this port only for high jitter systems and turn it off for typical applications.
(Simulation only) Specify PPM drift on the recovered clock(s) Specifies the amount of phase drift the LVDS SERDES IP simulation model adds to the recovered rx_divfwdclks.
Note: This feature will be supported in a future version of the Intel® Quartus® Prime software.
Table 29.  Receiver Settings Tab—Non-DPA Settings
Parameter Value Description
Desired receiver inclock phase shift (degrees)

Specifies, in degrees of the LVDS fast clock, the ideal phase delay of inclock with respect to transitions in the incoming serial data.

For example, specifying 180° implies that the inclock is center aligned to the incoming data.

Actual receiver inclock phase shift (degrees)

Depends on the fast_clock and inclock frequencies. Refer to the related information.

Specifies the closest achievable receiver inclock phase shift to the desired receiver inclock phase shift.

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