Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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4.3.4. Timing Closure Guidelines for Internal FPGA Paths

Closing timing at the internal FPGA paths is challenging for an LVDS SERDES design with high frequency and low SERDES factor.

If you observe setup violation from core registers to LVDS transmitter hardware, check the TX core registers clock parameter:

  • If the parameter is set to inclock, consider changing it to tx_coreclock. Core registers that use tx_coreclock have less clock delay. Because of the PLL compensation delay on the tx_coreclock path, there is less source clock delay and more setup slack for the transfer.
  • If the parameter is set to tx_coreclock, consider lowering the data rate or increasing the SERDES factor to reduce the core frequency requirement and provide more setup slack.

If you observe hold violation from the LVDS receiver to core registers, consider checking the setup slack of the transfer. If there is ample setup slack, you can attempt to over-constraint the hold for the transfer. Normally, the Fitter attempts to correct the hold violation by adding delay. Under certain circumstances, the Fitter may have calculated that adding more delay for avoiding hold violation at the fast corner can negatively affect setup at the slow corner.

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