Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

3.1.6.2. PLLs Driving DPA-Enabled Differential Receiver Channels

For differential receivers, the PLL can drive all channels in the same I/O bank but cannot drive across banks.

Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel. If you enable a DPA channel in a bank, you can assign the unused I/O pins in the bank to single-ended or differential I/O standards that has the same VCCIO voltage level used by the bank.

DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel® Quartus® Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.

Figure 19. PLLs Driving DPA-Enabled Differential Receiver Channels


Figure 20. Sharing Reference Clock Source to Differential Receiver Channels Across I/O Banks


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