Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

5.1.1. LVDS SERDES Intel® FPGA IP General Settings

Table 25.  General Settings Tab
Parameter Value Description
Duplex Feature
  • On
  • Off
Turn on to allow transmitter and receiver channels in the same I/O bank.
  • The number of transmitter and receiver channels in the same I/O bank is the same.
  • The number of channels is limited to 11 transmitters and 11 receivers.
  • Use external PLL option is disabled.
Functional mode
  • TX
  • RX Non-DPA
  • RX Soft-CDR

Specifies the functional mode of the interface.

The TX option is not available if you turn on the Duplex Feature option. In duplex mode, transmitter channels are created by default.

Number of channels
  • Duplex Feature = Off
    • TX—1 to 72
    • RX Non-DPA—1 to 24
    • RX DPA-FIFO—1 to 24
    • RX Soft-CDR—1 to 12
  • Duplex Feature = On
    • 1 to 11

Specifies the number of serial channels in the interface.

  • If you use a dedicated reference clock for the TX, RX non-DPA, or RX DPA-FIFO, you must use one of the channels for the refclk pin. Use a dedicated reference clock to reduce jitter.
  • If you use a transmitter output clock, you must use one of the channels for the tx_outclock pin.

For an LVDS RX design, place the refclk pin on the same I/O bank as the receiver.

For an LVDS TX design:

  • For an interface with less than 23 channels (standalone), each interface requires a refclk pin on the same I/O bank.
  • For an interface with more than 23 channels, channels 23 to 71 can share one refclk input.

In Duplex Feature mode, this value specifies the number of channels each for the transmitter and receiver. For example, if you specify 11 channels, the IP core uses 22 channels in the I/O bank.

Data rate 150.0 to 1600.0

Specifies the data rate (in Mbps) of a single serial channel. The value is dependent on the Functional mode parameter settings.

SERDES factor 3, 4, 5, 6, 7, 8, 9, and 10

Specifies the serialization rate or deserialization rate for the LVDS interface.

Use backwards-compatible port names
  • On
  • Off
Turn on to use legacy top-level names that are compatible with the ALTLVDS_TX and ALTLVDS_RX IPs.
Use the CPA block for improved periphery-core timing
  • On
  • Off
Turn on to improve timing closure between the periphery and core. The IP core uses the clock phase alignment (CPA) block to phase-align the core clock and load enable clock. The option is available for any selectable SERDES factor if:
  • Functional mode is TX, RX Non-DPA, or RX DPA-FIFO.
  • Desired tx_outclock phase shift (degrees) parameter is a multiple of 180°.