Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

2.5. Differential Receiver in Intel® Stratix® 10 Devices

The receiver has a differential buffer and I/O PLLs that you can share among the transmitter and receiver, a DPA block, a synchronizer, a data realignment block, and a deserializer. The differential buffer can receive LVDS, mini-LVDS, and RSDS signal levels. You can statically set the I/O standard of the receiver pins to LVDS, mini-LVDS, or RSDS in the Intel® Quartus® Prime software Assignment Editor.

Note: The PLL that drives the LVDS SERDES channel must operate in integer PLL mode. You do not need a PLL if you bypass the deserializer
Table 7.  Dedicated Circuitries and Features of the Differential Receiver
Dedicated Circuitry / Feature Description
Differential I/O buffer Supports LVDS, mini-LVDS, and RSDS
SERDES Up to 10-bit wide deserializer
Phase-locked loops (PLLs) Generates different phases of a clock for data synchronizer
Data realignment (Bit slip) Inserts bit latencies into serial data
DPA Chooses a phase closest to the phase of the serial data
Synchronizer (FIFO buffer) Compensate for phase differences between the data and the receiver’s input reference clock
Skew adjustment Manual
On-chip termination (OCT) 100 Ω in LVDS I/O standards

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