Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
Document Table of Contents

4.1.4.5. Clock Phase Alignment

The CPA block helps improve timing closure between the periphery and the core. To use this feature, turn on the Use the CPA block for improved periphery-core timing option in the LVDS SERDES IP core parameter editor.

If you turn on the option, the LVDS SERDES IP core uses the CPA block to phase-align the core clock and the load enable clock.

Table 20.  Core Clock Duty Cycles when Using the CPA FeatureThis table lists the actual core clock duty cycles if you turned on the Use the CPA block for improved periphery-core timing feature. The CPA feature works best for SERDES factors 4 and 8 where the core clock duty cycle remains 50%.
SERDES Factor Actual Core Clock Duty Cycle
3 66.6%
4 50%
5 40%
6 33%
7 40%
8 50%
9 40%
10 40%

The Use the CPA block for improved periphery-core timing option is available for any selectable SERDES factor under the following conditions:

  • The IP core functional mode is TX, RX Non-DPA, or RX DPA-FIFO.
  • The tx_outclock phase shift is a multiple of 180°.

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