Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

5.1.3.1. Receiver Input Clock Parameters Setup

To sample the source-synchronous data using the SERDES receiver in non-DPA mode, you must specify the phase relationship between the inclock and the rx_in data.

You can specify the inclock to rx_in phase relationship value in the Desired receiver inclock phase shift (degrees) parameter setting. The value must be evenly divisible by 45. If the value is not divisible by 45, the actual phase shift appears in the Actual receiver inclock phase shift (degrees) parameter setting.

Edge-Aligned inclock to rx_in

For rising inclock edge-aligned to the rx_in data, specify 0° as the desired receiver clock phase shift. Specifying 0° phase shift sets the PLL with the required phase shift from fast_clock to center it at the SERDES receiver.

Figure 42.  0° Edge-Aligned inclock x8 Deserializer Waveform with Single Rate Clock


The phase shift you specify is relative to the fast_clock, which operates at the serial data rate. Use phase shift values between 0° and 360° to specify the rising edge of the inclock within a single bit period. If you specify phase shift values greater than 360°, the MSB location within the parallel data changes.

This equation determines the maximum phase shift value: (Number of fast_clock periods per inclock period x 360) – 1.

Note: By default, the MSB from the serial data is not the MSB of the parallel data. You can use bit slip to set the proper word boundary on the parallel data.

Center-Aligned inclock to rx_in

To specify a center-aligned relationship between inclock and rx_in, specify a 180° phase shift.

Figure 43.  180° Center-Aligned inclock x8 Deserializer Waveform with Single Rate Clock


The inclock to rx_in phase shift relationship you specify is independent of the inclock frequency.

To specify a center-aligned DDR inclock to rx_in relationship, specify a 180° phase shift.

Figure 44.  180° Center Aligned inclock x8 Deserializer Waveform with DDR Clock


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