Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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4.1.4. LVDS SERDES IP Core Functional Description

You can configure each LVDS SERDES IP core channel as a receiver or a transmitter for a single differential I/O.

Each LVDS SERDES IP core channel contains a SERDES, a bitslip block, DPA circuitry for all modes, a high-speed clock tree (LVDS clock tree) and forwarded clock signal for soft-CDR mode. Therefore, an n-channel LVDS interface contains n-serdes_dpa blocks.

The I/O PLLs drive the LVDS clock tree, providing clocking signals to the LVDS SERDES IP core channel in the I/O bank.

Figure 33.  LVDS SERDES Channel Diagram


Table 17.   LVDS SERDES IP Core Channel Paths and Functional UnitsThis table lists the paths and seven functional units in each LVDS SERDES IP core channel.
Path Block Mode Clock Domain
TX Data Path Serializer TX LVDS
RX Data Path DPA
  • DPA-FIFO
  • Soft-CDR
DPA
DPA FIFO DPA-FIFO LVDS–DPA domain crossing
  • Bitslip
  • Deserializer
  • Non-DPA
  • DPA-FIFO
LVDS
Soft CDR DPA
Clock Generation and Multiplexers Local Clock Generator Soft-CDR Generates PCLK and load_enable in these modes
SERDES Clock Multiplexers All Selects LVDS clock sources for all modes

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