4.1.4. LVDS SERDES IP Core Functional Description
Each LVDS SERDES IP core channel contains a SERDES, a bitslip block, DPA circuitry for all modes, a high-speed clock tree (LVDS clock tree) and forwarded clock signal for soft-CDR mode. Therefore, an n-channel LVDS interface contains n-serdes_dpa blocks.
The I/O PLLs drive the LVDS clock tree, providing clocking signals to the LVDS SERDES IP core channel in the I/O bank.
|TX Data Path||Serializer||TX||LVDS|
|RX Data Path||DPA||
|DPA FIFO||DPA-FIFO||LVDS–DPA domain crossing|
|Clock Generation and Multiplexers||Local Clock Generator||Soft-CDR||Generates PCLK and load_enable in these modes|
|SERDES Clock Multiplexers||All||Selects LVDS clock sources for all modes|
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