Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
Document Table of Contents

4.1. LVDS SERDES Intel® FPGA IP

The LVDS SERDES IP configures the serializer/deserializer (SERDES) and dynamic phase alignment (DPA) blocks. The IP also supports LVDS channel placements, legality checks, and LVDS channel-related rule checks.

With the LVDS SERDES IP core, you can implement these types of LVDS applications:

  • Transmitter-only applications
  • Receiver-only applications
  • Applications with a mix of transmitters and receivers
Note: If you are migrating designs from Stratix® V, Arria® V, or Cyclone® V devices, you must migrate the ALTLVDS_TX and ALTLVDS_RX IP cores.

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