Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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3.1.7.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode

Figure 24. Non-DPA or DPA LVDS Receiver Interface with the IOPLL IP in External PLL Mode


Figure 25. Soft-CDR LVDS Receiver Interface with the IOPLL IP in External PLL Mode


Figure 26. LVDS Transmitter Interface with the IOPLL IP in External PLL ModeConnect the I/O PLL lvds_clk[1] and loaden[1] ports to the ext_fclk and ext_loaden ports of the LVDS transmitter.


The ext_coreclock port is automatically enabled in the LVDS SERDES IP in external PLL mode. The Intel® Quartus® Prime compiler outputs error messages if this port is not connected as shown in the preceding figures.

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