Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
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2.5.1. Receiver Blocks in Intel® Stratix® 10 Devices

The Intel® Stratix® 10 differential receiver has the following hardware blocks:

  • DPA block
  • Synchronizer
  • Data realignment block (bit slip)
  • Deserializer
Figure 8. Receiver Block DiagramThis figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic.


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