Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

2.5.1. Receiver Blocks in Intel® Stratix® 10 Devices

The Intel® Stratix® 10 differential receiver has the following hardware blocks:

  • DPA block
  • Synchronizer
  • Data realignment block (bit slip)
  • Deserializer
Figure 8. Receiver Block DiagramThis figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic.