Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 3/28/2022
Public
Document Table of Contents

2.5.2.1. Non-DPA Mode

The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is registered at the rising edge of the serial fast_clock clock that is produced by the I/O PLLs.

The fast_clock clock that is generated by the I/O PLLs clocks the data realignment and deserializer blocks.

Figure 13. Receiver Datapath in Non-DPA ModeThis figure shows the non-DPA datapath block diagram.


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