Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents

4.1.2. LVDS SERDES Intel® FPGA IP Features

The LVDS SERDES IP includes features for the LVDS receiver and transmitter. You can use the Intel® Quartus® Prime parameter editor to configure the LVDS SERDES IP.

The LVDS SERDES IP provides the following features for you to implement your LVDS I/O design:

  • Parameterizable data channel widths
  • Parameterizable SERDES factors
  • Registered input and output ports
  • PLL control signals
  • Non-DPA mode
  • DPA mode
  • Soft clock data recovery (CDR) mode
  • Duplex mode—transmitters and receivers in the same I/O bank
  • Clock phase alignment (CPA) block