Intel® Stratix® 10 High-Speed LVDS I/O User Guide

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ID 683792
Date 3/28/2022
Public
Document Table of Contents

4.4.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples

The synthesizable design example is a compilation-ready Platform Designer system that you can include in an Intel® Quartus® Prime project.

The design example uses the parameter settings you configured in the IP parameter editor:

  • Basic LVDS SERDES IP system with transmitters or receivers
  • Duplex LVDS SERDES IP system with transmitters and receivers
  • LVDS SERDES IP system with transmitters or receivers connected to an external PLL
Figure 37. Basic LVDS SERDES IP System with Internal PLL


If you configured the IP to use an external PLL, the generated design example connects a properly configured IOPLL Intel® FPGA IP.

Figure 38.  LVDS SERDES IP System with External PLLIn this figure, a qsys_interface_bridge provides Platform Designer connections between the IOPLL IP and the LVDS SERDES IP. For simplicity, this bridge is not shown in the other figures.


To demonstrate how to configure the PLL, the design example also provides the lvds_external_pll.qsys Platform Designer file containing a standalone version of the IOPLL IP configured to work as an external PLL. You can use lvds_external_pll.qsys, modified or unmodified, to build an LVDS design with external PLL.

Generating and Using the Design Example

To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory:

quartus_sh -t make_qii_design.tcl -system ed_synth

The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.

For more information about make_qii_design.tcl arguments, run the following command:

quartus_sh -t make_qii_design.tcl -help

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