Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Public
Document Table of Contents
Give Feedback

2.4.2. Serializer Bypass for DDR and SDR Operations

The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR mode.

You can bypass the serializer to support DDR (x2) and SDR (x1) operations to achieve a serialization factor of 2 and 1, respectively. The deserializer bypass is supported through the GPIO Intel® FPGA IP.

Figure 7. Serializer BypassThis figure shows the serializer bypass path.


  • In SDR mode:
    • The IOE data width is 1 bit.
    • Registered output path requires a clock.
    • Data is passed directly through the IOE.
  • In DDR mode:
    • The IOE data width is 2 bits.
    • The GPIO IP core requires a clock.
    • tx_inclock clocks the IOE register.