Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents Deserializer

The deserializer consists of shift registers. The deserialization factor determines the depth of the shift registers. The deserializer converts a 1-bit serial data stream into a parallel data stream based on the deserialization factor.

The load_enable is a pulse signal with a frequency equivalent to the fast clock divided by the deserialization factor.

Figure 35.  LVDS x8 Deserializer Waveform

Table 19.  LVDS Deserializer Signals
Signal Description
rx_in LVDS input data stream to the LVDS SERDES IP core channel
fast_clock Clock for the receiver
load_enable Enable signal for deserialization
rx_out[7:0] Deserialized data