Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 11/30/2022
Document Table of Contents DPA Mode

The DPA block chooses the best possible clock (dpa_fast_clock) from the eight fast clocks that the I/O PLL sent. This serial dpa_fast_clock clock is used for writing the serial data into the synchronizer. A serial fast_clock clock is used for reading the serial data from the synchronizer. The same fast_clock clock is used in data realignment and deserializer blocks.

Figure 14. Receiver Datapath in DPA Mode This figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active.

Note: In DPA mode, you must place all receiver channels of an LVDS instance in one I/O bank. Because each I/O bank has a maximum of 24 LVDS I/O buffer pairs, each LVDS instance can support a maximum of 24 DPA channels.